The invention relates to a method and apparatus for digital clock recovery, in particular for a packet oriented network environment.
An example of a packet oriented transmission technology for the realization of Broadband Integrated Service Networks (BISDN) is the technology called Asynchronous Transfer Mode (ATM). This permits services as diverse as voice, data and video to be transmitted through the same medium and in the same format. The transport of constant bit rate (CBR) data over an ATM network is usually referred to as circuit emulation. The accommodation of constant bit rate (CBR) services by ATM is particularly important, for compatibility with existing systems and future networks, even if ATM is more suitable to the transport of bursty traffic, such as data. One of the critical issues of circuit emulation is the recovery of clock frequency of the source data (the service clock frequency) at the receiver.
ATM""s basic transport entity is a 53 byte cell. Five of these bytes are header bytes, and convey information such as link-to-link routing, error correction, service information (priority, payload identifier), and cell type identification. A protocol stack is defined by ITU-T for ATM technology, in which the so-called ATM layer performs operations typically found in layers 2 and 3 of the OSI model. Above the ATM layer is an ATM adaptation layer (AAL), which is divided into segmentation and reassembling layers (SAR) and a convergence sublayer (CS). Five different types of AAL have been defined by ITU-T, covering various applications. The AAL-1 (ATM Adaptation Layer 1) is devoted to CBR services. Of the 48 remaining information bytes of an ATM cell, one used by the AAL1 SAR for functions including timing recovery and cell loss detection which leaves 47 data bytes (376 bits). To transport a CBR service into an ATM network, the data is segmented into cells of 47 bytes, an SAR byte is then added to each cell, the 48 bytes are mapped in an ATM cell and are then sent through the network.
As a result of statistical multiplexing of cells at the source and of queuing delays incurred in ATM switches, successive cells arrive to the destination aperiodically. The deviation from ideal arrival time is called cell jitter or cell delay variation (CDV). It obviously increases with the network load, as queuing delays are functions of the switch load. Cell jitter is composed of a relatively high frequency stuffing jitter and of a low frequency waiting time jitter. The problem with cell jitter is that it can be very large, and except for the fact that its average is zero, its characteristics are mostly unknown.
The ITU-T has set output clock jitter recommendations whereby the frequency shift at 2.048 MHz on emission clocks is +/xe2x88x9250 ppm (1 ppm=1 part per million=2.048 Hz shift).
In order to achieve clock recovery, the exact service frequency should be recovered at the receiver. However, this is not straightforward due to the problems of output jitter and wander control. Jitter is defined as the higher frequency characteristics of a phase variation on a given clock signal. Wander is the lower frequency part of this phase variation. Both are commonly measured in terms of unit intervals (UI), where one UI corresponds to one cycle of the clock signal. ITU-T recommendation G.823 has precisely defined output jitter limits that must be met if the system is to be compatible with any CBR equipment. The bounds on maximum peak-to-peak output jitter for 2.048 Mbits.sxe2x88x921 CBR services are shown in Table 1.
Wander tolerance is not as well defined as output jitter. However, input jitter should not be greater than 36.9 UI under 1.2xc3x9710xe2x88x925 Hz.
Two techniques are known for recovering a service, or emission clock at a receiver. A first technique, known as the xe2x80x9cadaptive methodxe2x80x9d, recovers the service clock based on the fill-level of a incoming cell buffer. A second technique, known as the xe2x80x9csynchronous methodxe2x80x9d is based on the availability of a common network reference clock between the source and the end equipment.
The common clock used in the synchronous method is distributed by the network, and is available by means of either the so-called Synchronous Digital Hierarchy (SDH) network or its North American version Synchronous Optical NETwork (SONET). As not all CBR equipment is able or willing to be synchronized at the network clock, a method exists to perform CBR transmission at any rate, using this network clock. The method which was first proposed by Bell Laboratories and then adopted by ITU-T is the so-called synchronous residual time stamps (SRTS) technique. This allows transmission at any given bit rate.
The SRTS technique uses the network common clock to generate a unique number (the SRTS, or Synchronous Residual Time Stamp) which, on receipt, is used to recover the service clock. This information is inserted into the SAR byte (the 48th byte) and sent to an ATM cell. Using this common clock completely eliminates the cell jitter problem, as the actual cell arrival instants are not taken into account when recovering the service clock.
FIG. 1 of the accompanying drawings is a schematic block diagram illustrating an example of an SRTS signal generator 10.
The service clock 12 (at frequency fs) is divided by an integer N in a first divider 16. The integer N represents the SRTS period and is typically a multiple of 376, as an ATM cell conveys 47 information bytes, that is 47xc3x978=376 bits. ITU-T recommends that the SRTS 24 is coded on 4 bits. As the SRTS is transported by the SAR byte, and only one bit every two cells can be devoted to SRTS, 8 cells are necessary to convey one time stamp, which leads to a preferred value of N=8xc3x97376=3008. The output of the first divider 16 is used as a latching signal to a latch 20 for latching the output of a p-bit free running counter 22, driven by a submultiple fnx of the network clock 14. The output of the latch 20 forms the SRTS 24.
The submultiple fnx of the network clock is generated by dividing the network clock 14 (at the network frequency fn) by a divider x in a second divider 18. The division ratio x is chosen so that the ratio fs/fnx stays over 1 but under 2 in order to reduce jitter and wander on the recovered clock. The value of the network clock depends on the type of network. For SDH network, fn is 155.52 MHz, so fnx will be of the form 155.52/2k. For 2.048 MHz clock recovery, k equals 6, and fnx 2.43 MHz. The SONET network referenced above distributes a 51.84 MHz clock, which leads to a value for fnx of 3.24 MHz.
During a SRTS period (=Nfs clock periods), there are M cycles of the fnx clock. Generally, M is not an integer. The information conveyed by the SRTS 24 is the number of cycle slips between the two clocks at frequency fs and fnx, modulus 2p over a SRTS period (=N periods of the fs clock), rounded towards zero. The residual part, corresponding to the fact that M is not an integer, accumulates until it reaches unity.
FIG. 2 of the accompanying drawings is a schematic block diagram of an SRTS receiver 30 for implementing a known technique to recover the service clock using the SRTS 24. The SRTS receiver 30 comprises an SRTS buffer 32 in which received SRTSs are buffered. An output 24 from the SRTS buffer 32 is supplied to one input of a comparator 34. The other input to the comparator is connected to the output of a free running p-bit counter 36 (locally generated SRTS) which is driven by an fnx clock 38. The output of the comparator and the fnx clock are supplied to a gating circuit 40. The output of the gating circuit is supplied to a phase locked loop (PLL) 42. The output of the PLL 42 forms the clock fs.
In order to illustrate the operation of the SRTS receiver 30 of FIG. 2, it is assumed that the PLL 42 is locked, the gating circuit 40 has just been reset, and a new SRTS 24 has just been extracted from the SRTS buffer 32. The SRTS 24 which has been extracted is supplied to the comparator 34, where it is compared to the output of the free running p-counter 36 driven by the fnx clock 38. A pulse is generated each time the output of the counter 36 matches the received SRTS 24. One of these pulses will give the correct SRTS period. However, it is necessary to determine which of these pulses is the correct one.
A train of pulses from the comparator 34, represented at (a) in FIG. 3, is then fed to the gating circuit 40, which determines which pulse is the correct one. The value of p for the p-bit counter 36 is chosen such that a SRTS 24 represents with no ambiguity a SRTS period. Accordingly, it is known that the correct pulse will occur after a minimum of Mmin pulses of the fnx clock. The gating circuit comprises a counter 48, which receives a gating pulse, represented at (b) in FIG. 3 from a pulse forming circuit 46. The pulse forming circuit 46 is responsive to the output of a counter 44. The counter 44 is arranged to count until Mmin fnx periods have elapsed and then to generate an output synchronised with each correct SRTS. The output of the gate 48, as represented at (c) in FIG. 3, thus gives the real SRTS period. The PLL 42 generates N pulses between two successive pulses output from the gating circuit, the output of the PLL 42 thus represents the service clock fs.
The prior art SRTS technique described above is, however, not an exact technique as it quantifies the difference between the service and network clock. Accordingly, a disadvantage of this technique is that it introduces an error by multiplying the gating circuit output by N, as N+/xe2x88x92e pulses of the service clock between two SRTS pulse intervals.
Accordingly, there is a need to provide an improved technique for recovering a service clock frequency using an SRTS.
In accordance with one aspect of the present invention, there is provided a clock recovery mechanism for an ATM receiver for recovering a service clock transmitted over an ATM network, the mechanism comprising: an input for receiving an SRTS from the ATM network; a local SRTS generator for locally generating an SRTS; a comparator for comparing a received SRTS and a locally generated SRTS; and a recovered service clock generator responsive to an output of the comparator for generating the recovered service clock and for controlling the local SRTS generator.
An embodiment of the invention enables a locally generated SRTS to be compared directly with the received SRTS. The local SRTS is generated using the same method as used to generate the transmitted SRTS, that is using the network clock fnx and a locally generated clock, at frequency fs. The difference between the locally generated SRTS and the received SRTS can be expressed directly in a number of fnx pulse clocks to be added or removed to the generated fs clock. An embodiment of the present invention can thus provide a digital technique for recovering a service (or source) clock at the receiver location using SRTSs.
Preferably, the local SRTS generator is controllable in response to the recovered service clock. More preferably, the local SRTS generator comprises a divider for dividing the recovered service clock by N. Preferably, the local SRTS generator has a structure which mirrors that of an SRTS generator at an ATM transmitter.
In a preferred embodiment, the local SRTS generator comprises: a latch, an output of which provides the locally generated SRTS; a p-bit free running counter, driven by a submultiple of an ATM network clock, the latch being connected to receive an output from the counter; and a divider having an output connected to a latch input of the latch for latching the output from the counter and an input connected to receive the recovered service clock, the divider outputting the recovered service clock divided by N. This structure corresponds to an STRS generator for an ATM transmitter. In one embodiment, N is 3008 to provide an SRTS period.
Preferably, the recovered service clock generator comprises a controller and a digitally controlled oscillator; the controller comprises an input connected to the comparator, and an output connected to a control input of the digitally controlled oscillator, the controller outputting control signals for controlling the digitally controlled oscillator; and the digitally controlled oscillator has an output for the recovered service clock, the digitally controlled oscillator outputting the recovered service clock under the control of the control signals at the control input.
In a preferred embodiment, the controller comprises a look-up table, the controller being responsive to the comparator outputs for accessing control signals from the look-up table for output to the digitally controlled oscillator.
Preferably, the input for receiving an SRTS from the ATM network comprises an SRTS buffer for buffering received STRSs.
The invention also provides an ATM receiver circuit comprising a mechanism as set out above.
The invention further provides an ATM receiver comprising a mechanism as set out above.
In accordance with another aspect of the invention, there is provided a clock recovery method at an ATM receiver for recovering a service clock transmitted over an ATM network, the method comprising:
receiving an SRTS from the ATM network;
generating locally an SRTS;
comparing a received SRTS and a locally generated SRTS; and
generating a recovered service clock in response to an output of the comparator and using the recovered service clock to control the local SRTS generation.
In accordance with a further aspect of the invention there is provided a method of circuit emulation over an ATM network comprising, at an ATM transmitter, using a first SRTS generator for generating SRTSs for transmission in response to a CBR service clock and, at an ATM receiver:
receiving SRTSs from the ATM network;
generating locally SRTSs using a second SRTS generator equivalent to the first SRTS generator;
comparing the received SRTSs and the locally generated SRTSs; and
generating a recovered CBR service clock in response to an output of the comparator and using the recovered CBR service clock to control the local SRTS generation.